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LT1160/LT1162 Half-/Full-Bridge N-Channel Power MOSFET Drivers
FEATURES

DESCRIPTIO
Floating Top Driver Switches Up to 60V Drives Gate of Top N-Channel MOSFET above Load HV Supply 180ns Transition Times Driving 10,000pF Adaptive Nonoverlapping Gate Drives Prevent Shoot-Through Top Drive Protection at High Duty Cycles TTL/CMOS Input Levels Undervoltage Lockout with Hysteresis Operates at Supply Voltages from 10V to 15V Separate Top and Bottom Drive Pins
The LT (R)1160/LT1162 are cost effective half-/full-bridge N-channel power MOSFET drivers. The floating driver can drive the topside N-channel power MOSFETs operating off a high voltage (HV) rail of up to 60V. The internal logic prevents the inputs from turning on the power MOSFETs in a half-bridge at the same time. Its unique adaptive protection against shoot-through currents eliminates all matching requirements for the two MOSFETs. This greatly eases the design of high efficiency motor control and switching regulator systems. During low supply or start-up conditions, the undervoltage lockout actively pulls the driver outputs low to prevent the power MOSFETs from being partially turned on. The 0.5V hysteresis allows reliable operation even with slowly varying supplies. The LT1162 is a dual version of the LT1160 and is available in a 24-pin PDIP or in a 24-pin SO Wide package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

PWM of High Current Inductive Loads Half-Bridge and Full-Bridge Motor Control Synchronous Step-Down Switching Regulators 3-Phase Brushless Motor Drive High Current Transducer Drivers Class D Power Amplifiers
TYPICAL APPLICATIO
1N4148
HV = 60V MAX
+
12V 10F 25V 1 10 SV
+
BOOST T GATE DR T GATE FB
14 13 12 11 CBOOST 1F IRFZ44
1000F 100V
PV +
4
UV OUT
T SOURCE
LT1160 2 PWM 0Hz TO 100kHz 3 IN TOP IN BOTTOM SGND 5 B GATE DR B GATE FB PGND 6 9 8 IRFZ44
IN TOP IN BOTTOM T GATE DR B GATE DR L L H H L H L H L L H L L H L L
1160 TA01
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LT1160/LT1162
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Note 2) ......................................... 20V Boost Voltage ......................................................... 75V Peak Output Currents (< 10s) .............................. 1.5A Input Pin Voltages .......................... - 0.3V to V + + 0.3V Top Source Voltage ..................................... - 5V to 60V Boost to Source Voltage ........................... - 0.3V to 20V Operating Temperature Range Commercial .......................................... 0C to 70C Industrial ......................................... - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW SV + 1 IN TOP 2 IN BOTTOM 3 UV OUT 4 SGND 5 PGND 6 NC 7 N PACKAGE 14-LEAD PDIP S PACKAGE 14-LEAD PLASTIC SO 14 BOOST 13 T GATE DR 12 T GATE FB 11 T SOURCE 10 PV + 9 B GATE DR 8 B GATE FB
ORDER PART NUMBER LT1160CN LT1160CS LT1160IN LT1160IS
TJMAX = 125C, JA = 70C/ W (N) TJMAX = 125C, JA = 110C/ W (S)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER IS DC Supply Current (Note 4)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test Circuit, TA = 25C, V + = VBOOST = 12V, VTSOURCE = 0V, CGATE = 3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.
CONDITIONS V + = 15V, VINTOP = 0.8V, VINBOTTOM = 2V V + = 15V, VINTOP = 2V, VINBOTTOM = 0.8V V + = 15V, VINTOP = 0.8V, VINBOTTOM = 0.8V V + = 15V, VTSOURCE = 60V, VBOOST = 75V, VINTOP = VINBOTTOM = 0.8V

IBOOST VIL VIH IIN V +UVH V +UVL VBUVH VBUVL
Boost Current (Note 4) Input Logic Low Input Logic High Input Current V + Undervoltage Start-Up Threshold V + Undervoltage Shutdown Threshold VBOOST Undervoltage Start-Up Threshold VBOOST Undervoltage Shutdown Threshold
VINTOP = VINBOTTOM = 4V
VTSOURCE = 60V (VBOOST - VTSOURCE) VTSOURCE = 60V (VBOOST - VTSOURCE)
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TOP VIEW SV
+A
1
24 BOOST A 23 T GATE DR A 22 T GATE FB A 21 T SOURCE A 20 PV + A 19 B GATE DR A 18 BOOST B 17 T GATE DR B 16 T GATE FB B 15 T SOURCE B 14 PV + B 13 B GATE DR B SW PACKAGE 24-LEAD PLASTIC SO WIDE
ORDER PART NUMBER LT1162CSW LT1162ISW
IN TOP A 2 IN BOTTOM A 3 UV OUT A 4 GND A 5 B GATE FB A 6 SV + B 7 IN TOP B 8 IN BOTTOM B 9 UV OUT B 10 GND B 11 B GATE FB B 12 N PACKAGE 24-LEAD PDIP
OBSOLETE PART NUMBERS LT1162CN LT1162IN
TJMAX = 125C, JA = 58C/ W (N) TJMAX = 125C, JA = 80C/ W (SW)
MIN 7 7 7 3
TYP 11 10 11 4.5 1.4
MAX 15 15 15 6 0.8 25 9.7 8.8 9.8 9.2
UNITS mA mA mA mA V V A V V V V
2 8.4 7.8 8.8 8.2
1.7 7 8.9 8.3 9.3 8.7
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LT1160/LT1162
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.Test Circuit, TA = 25C, V + = VBOOST = 12V, VTSOURCE = 0V, CGATE = 3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.
SYMBOL PARAMETER IUVOUT VUVOUT VOH VOL tr Undervoltage Output Leakage Undervoltage Output Saturation Top Gate ON Voltage Bottom Gate ON Voltage Top Gate OFF Voltage Bottom Gate OFF Voltage Top Gate Rise Time Bottom Gate Rise Time tf Top Gate Fall Time Bottom Gate Fall Time t D1 Top Gate Turn-On Delay Bottom Gate Turn-On Delay t D2 Top Gate Turn-Off Delay Bottom Gate Turn-Off Delay t D3 Top Gate Lockout Delay Bottom Gate Lockout Delay t D4 Top Gate Release Delay Bottom Gate Release Delay CONDITIONS V+ V+ = 15V = 7.5V, IUVOUT = 2.5mA

ELECTRICAL CHARACTERISTICS
MIN
TYP 0.1 0.2
MAX 5 0.4 12 12 0.7 0.7 200 200 140 140 500 400 600 400 600 500 500 400
UNITS A V V V V V ns ns ns ns ns ns ns ns ns ns ns ns
VINTOP = 2V, VINBOTTOM = 0.8V VINTOP = 0.8V, VINBOTTOM = 2V VINTOP = 0.8V, VINBOTTOM = 2V VINTOP = 2V, VINBOTTOM = 0.8V VINTOP (+) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 5) VINBOTTOM (+) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 5) VINTOP (-) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 5) VINBOTTOM (-) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 5) VINTOP (+) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 5) VINBOTTOM (+) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 5) VINTOP (-) Transition, VINBOTTOM = 0.8V, Measured at VTGATE DR (Note 5) VINBOTTOM (-) Transition, VINTOP = 0.8V, Measured at VBGATE DR (Note 5) VINBOTTOM (+) Transition, VINTOP = 2V, Measured at VTGATE DR (Note 5) VINTOP (+) Transition, VINBOTTOM = 2V, Measured at VBGATE DR (Note 5) VINBOTTOM (-) Transition, VINTOP = 2V, Measured at VTGATE DR (Note 5) VINTOP (-) Transition, VINBOTTOM = 2V, Measured at VBGATE DR (Note 5)
11 11
11.3 11.3 0.4 0.4 130 90 60 60 250 200 300 200 300 250 250 200
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: For the LT1160, Pins 1, 10 should be connected together. For the LT1162, Pins 1, 7, 14, 20 should be connected together. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LT1160CN/LT1160IN: TJ = TA + (PD)(70C/W) LT1160CS/LT1160IS: TJ = TA + (PD)(110C/W) LT1162CN/LT1162IN: TJ = TA + (PD)(58C/W) LT1162CS/LT1162IS: TJ = TA + (PD)(80C/W)
Note 4: IS is the sum of currents through SV +, PV + and Boost pins. IBOOST is the current through the Boost pin. Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Typical Performance Characteristics and Applications Information sections. The LT1160 = 1/2 LT1162. Note 5: See Timing Diagram. Gate rise times are measured from 2V to 10V and fall times are measured from 10V to 2V. Delay times are measured from the input transition to when the gate voltage has risen to 2V or decreased to 10V.
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LT1160/LT1162 TYPICAL PERFORMANCE CHARACTERISTICS
DC Supply Current vs Supply Voltage
14 13 14 13 V + = 12V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
11 10 9 8 7 6 5 8 10 12 14 16 18 SUPPLY VOLTAGE (V) 20 22 VINTOP = HIGH VINBOTTOM = LOW VINTOP = LOW VINBOTTOM = HIGH
11 10 9 8 7 6 5 -50 VINTOP = HIGH VINBOTTOM = LOW BOTH INPUTS HIGH OR LOW
SUPPLY CURRENT (mA)
12
BOTH INPUTS HIGH OR LOW
DC + Dynamic Supply Current vs Input Frequency
60 50 SUPPLY CURRENT (mA) 40 CGATE = 10000pF 30 20 10 0 CGATE = 3000pF 50% DUTY CYCLE V+ = 12V SUPPLY VOLTAGE (V)
11 10 START-UP THRESHOLD 9 8 7 6
CGATE = 1000pF 1 10 100 INPUT FREQUENCY (kHz) 1000
1160/62 G04
VBOOST - VTSOURCE VOLTAGE (V)
Input Threshold Voltage vs Temperature
2.0 V + = 12V 14 13 VHIGH 12
INPUT THRESHOLD VOLTAGE (V)
1.8 1.6
INPUT CURRENT (A)
11 10 9 8 7 6 5
INPUT CURRENT (mA)
VLOW 1.4 1.2 1.0 0.8 -50
-25
0 25 50 75 TEMPERATURE (C)
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UW
1160/62 G01
(LT1160 or 1/2 LT1162) DC + Dynamic Supply Current vs Input Frequency
60 50 40 30 20 V + = 10V 10 0 50% DUTY CYCLE CGATE = 3000pF
DC Supply Current vs Temperature
12
VINTOP = LOW VINBOTTOM = HIGH
V + = 20V V + = 15V
-25
0 25 50 75 TEMPERATURE (C)
100
125
1
10 100 INPUT FREQUENCY (kHz)
1000
1160/62 G03
1160/62 G02
Undervoltage Lockout (V +)
13 12
13 12 11 10 9 8 7 6 5
Undervoltage Lockout (VBOOST)
VTSOURCE = 60V
START-UP THRESHOLD
SHUTDOWN THRESHOLD
SHUTDOWN THRESHOLD
5 4 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
4 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1160/62 G05
1160/62 G06
Top or Bottom Input Pin Current vs Temperature
5.0 V + = 12V VIN = 4V 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -25 50 25 0 75 TEMPERATURE (C) 100 125 0
Top or Bottom Input Pin Current vs Input Voltage
V + = 12V
100
125
4 -50
4
5
6
10 8 7 9 INPUT VOLTAGE (V)
11
12
1160/62 G07
1160/62 G08
1160/62 G09
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LT1160/LT1162 TYPICAL PERFORMANCE CHARACTERISTICS
Bottom Gate Rise Time vs Temperature
230 210 V + = 12V
BOTTOM GATE FALL TIME (ns)
BOTTOM GATE RISE TIME (ns)
TOP GATE RISE TIME (ns)
190 170 150 130 110 90 70 50 -50
CLOAD = 10000pF
CLOAD = 3000pF CLOAD = 1000pF -25 0 25 50 75 TEMPERATURE (C) 100 125
Top Gate Fall Time vs Temperature
180 160 TOP GATE FALL TIME (ns) 140 120 100 80 60 40 CLOAD = 1000pF 20 -50 -25 0 25 50 75 100 125 CLOAD = 3000pF V + = 12V CLOAD = 10000pF TURN ON DELAY TIME (ns)
350 300 400
TURN OFF DELAY TIME (ns)
TEMPERATURE (C)
11160/62 G13
Lockout Delay Time vs Temperature
400 350 V + = 12V CLOAD = 3000pF 400 350 TOP DRIVER BOTTOM DRIVER
LOCKOUT DELAY TIME (ns)
300 250 200 150 100 -50
RELEASE DELAY TIME (ns)
-25
UW
1160/62 G10
(LT1160 or 1/2 LT1162) Top Gate Rise Time vs Temperature
300 280 260 240 220 200 180 160 140 120 100 CLOAD = 1000pF -25 0 25 50 75 TEMPERATURE (C) 100 125 80 -50 CLOAD = 3000pF V + = 12V CLOAD = 10000pF
Bottom Gate Fall Time vs Temperature
210 190 170 150 130 110 90 70 50 30 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 CLOAD = 3000pF CLOAD = 1000pF CLOAD = 10000pF V + = 12V
1160/62 G11
1160/62 G12
Turn-On Delay Time vs Temperature
400 V + = 12V CLOAD = 3000pF 350 300 250 200 150
Turn-Off Delay Time vs Temperature
V + = 12V CLOAD = 3000pF
TOP DRIVER
TOP DRIVER 250 200 BOTTOM DRIVER 150 100 -50
BOTTOM DRIVER
-25
0 25 50 75 TEMPERATURE (C)
100
125
100 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1160/62 G14
1160/62 G15
Release Delay Time vs Temperature
V + = 12V CLOAD = 3000pF
300 TOP DRIVER 250 200 BOTTOM DRIVER 150 100 -50
0 25 50 75 TEMPERATURE (C)
100
125
-25
0 25 50 75 TEMPERATURE (C)
100
125
1160/62 G16
1160/62 G17
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LT1160/LT1162
PIN FUNCTIONS
LT1160
SV+ (Pin 1): Main Signal Supply. Must be closely decoupled to the signal ground Pin 5. IN TOP (Pin 2): Top Driver Input. Pin 2 is disabled when Pin 3 is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. IN BOTTOM (Pin 3): Bottom Driver Input. Pin 3 is disabled when Pin 2 is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. UV OUT (Pin 4): Undervoltage Output. Open collector NPN output which turns on when V + drops below the undervoltage threshold. SGND (Pin 5): Small Signal Ground. Must be routed separately from other grounds to the system ground. PGND (Pin 6): Bottom Driver Power Ground. Connects to source of bottom N-channel MOSFET. B GATE FB (Pin 8): Bottom Gate Feedback. Must connect directly to the bottom power MOSFET gate. The top MOSFET turn-on is inhibited until Pin 8 has discharged to below 2.5V. B GATE DR (Pin 9): Bottom Gate Drive. The high current drive point for the bottom MOSFET. When a gate resistor is used it is inserted between Pin 9 and the gate of the MOSFET. PV + (Pin 10): Bottom Driver Supply. Must be connected to the same supply as Pin 1. T SOURCE (Pin 11): Top Driver Return. Connects to the top MOSFET source and the low side of the bootstrap capacitor. T GATE FB (Pin 12): Top Gate Feedback. Must connect directly to the top power MOSFET gate. The bottom MOSFET turn-on is inhibited until V12 - V11 has discharged to below 2.9V. T GATE DR (Pin 13): Top Gate Drive. The high current drive point for the top MOSFET. When a gate resistor is used it is inserted between Pin 13 and the gate of the MOSFET. BOOST (Pin 14): Top Driver Supply. Connects to the high side of the bootstrap capacitor.
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LT1162
SV + (Pins 1, 7): Main Signal Supply. Must be closely decoupled to ground Pins 5 and 11. IN TOP (Pins 2, 8): Top Driver Input. The Input Top is disabled when the Input Bottom is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. IN BOTTOM (Pins 3, 9): Bottom Driver Input. The Input Bottom is disabled when the Input Top is high. A 3k input resistor followed by a 5V internal clamp prevents saturation of the input transistors. UV OUT (Pins 4, 10): Undervoltage Output. Open collector NPN output which turns on when V + drops below the undervoltage threshold. GND (Pins 5, 11): Ground Connection. B GATE FB (Pins 6, 12): Bottom Gate Feedback. Must connect directly to the bottom power MOSFET gate. The top MOSFET turn-on is inhibited until Bottom Gate Feedback pins have discharged to below 2.5V. B GATE DR (Pins 13, 19): Bottom Gate Drive. The high current drive point for the bottom MOSFET. When a gate resistor is used it is inserted between the Bottom Gate Drive pin and the gate of the MOSFET. PV + (Pins 14, 20): Bottom Driver Supply. Must be connected to the same supply as Pins 1 and 7. T SOURCE (Pins 15, 21): Top Driver Return. Connects to the top MOSFET source and the low side of the bootstrap capacitor. T GATE FB (Pins 16, 22): Top Gate Feedback. Must connect directly to the top power MOSFET gate. The bottom MOSFET turn-on is inhibited until VTGF - VTSOURCE has discharged to below 2.9V. T GATE DR (Pins 17, 23): Top Gate Drive. The high current drive point for the top MOSFET. When a gate resistor is used it is inserted between the Top Gate Drive pin and the gate of the MOSFET. BOOST (Pins 18, 24): Top Driver Supply. Connects to the high side of the bootstrap capacitor.
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LT1160/LT1162
FUNCTIONAL DIAGRA W U U
(LT1160 or 1/2 LT1162)
BOOST TOP UV LOCK SV +
BIAS T GATE DR 3k
5V 2.9V T SOURCE 3k IN BOTTOM 5V PV +
BOTTOM UV LOCK UV OUT
SGND LT1160 PGND 1/2 LT1162 GND B GATE FB
1160/62 BD
TEST CIRCUIT
+
V/I
(LT1160 or 1/2 LT1162)
SV + 1F 3k IN TOP IN BOTTOM UV OUT
BOOST T GATE DR T GATE FB T SOURCE PV +
(LT1160) 50 50 SGND PGND B GATE DR B GATE FB
-
+
B GATE DR
IN TOP
- +
2.5V
T GATE FB
+
V/I
+
V
3000pF
1F
+
V
+
V
3000pF
1160/62 TC01
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LT1160/LT1162 TI I G DIAGRA
2V IN TOP 0.8V
2V IN BOTTOM 0.8V tr 12V TOP GATE DRIVER 0V tr 12V BOTTOM GATE DRIVER 0V t D1 10V 2V tf t D4
1160/62 TD
OPERATIO
(Refer to Functional Diagram)
The LT1160 (or 1/2 LT1162) incorporates two independent driver channels with separate inputs and outputs. The inputs are TTL/CMOS compatible; they can withstand input voltages as high as V+. The 1.4V input threshold is regulated and has 300mV of hysteresis. Both channels are noninverting drivers. The internal logic prevents both outputs from simultaneously turning on under any input conditions. When both inputs are high both outputs are actively held low. The floating supply for the top driver is provided by a bootstrap capacitor between the Boost pin and the Top Source pin. This capacitor is recharged each time the negative plate goes low in PWM operation. The undervoltage detection circuit disables both channels when V + is below the undervoltage trip point. A separate
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t D3 10V 2V t D1 t D3 t D2 tf t D4 t D2
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UV detect block disables the high side channel when VBOOST - VTSOURCE is below its own undervoltage trip point. The top and bottom gate drivers in the LT1160 each utilize two gate connections: 1) a gate drive pin, which provides the turn on and turn off currents through an optional series gate resistor, and 2) a gate feedback pin which connects directly to the gate to monitor the gate-to-source voltage. Whenever there is an input transition to command the outputs to change states, the LT1160 follows a logical sequence to turn off one MOSFET and turn on the other. First, turn-off is initiated, then VGS is monitored until it has decreased below the turn-off threshold, and finally the other gate is turned on.
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LT1160/LT1162
APPLICATIONS INFORMATION
Power MOSFET Selection Since the LT1160 (or 1/2 LT1162) inherently protects the top and bottom MOSFETs from simultaneous conduction, there are no size or matching constraints. Therefore selection can be made based on the operating voltage and RDS(ON) requirements. The MOSFET BVDSS should be greater than the HV and should be increased to approximately (2)(HV) in harsh environments with frequent fault conditions. For the LT1160 maximum operating HV supply of 60V, the MOSFET BVDSS should be from 60V to 100V. The MOSFET RDS(ON) is specified at TJ = 25C and is generally chosen based on the operating efficiency required as long as the maximum MOSFET junction temperature is not exceeded. The dissipation while each MOSFET is on is given by: P = D(IDS)2(1+)RDS(ON) Where D is the duty cycle and is the increase in RDS(ON) at the anticipated MOSFET junction temperature. From this equation the required RDS(ON) can be derived:
R DS(ON) = P D IDS
( ) (1+ )
2
For example, if the MOSFET loss is to be limited to 2W when operating at 5A and a 90% duty cycle, the required RDS(ON) would be 0.089/(1 + ). (1 + ) is given for each MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.007/C can be used as an approximation for low voltage MOSFETs. Thus, if TA = 85C and the available heat sinking has a thermal resistance of 20C/W, the MOSFET junction temperature will be 125C and = 0.007(125 - 25) = 0.7. This means that the required RDS(ON) of the MOSFET will be 0.089/1.7 = 0.0523, which can be satisfied by an IRFZ34 manufactured by International Rectifier. Transition losses result from the power dissipated in each MOSFET during the time it is transitioning from off to on, or from on to off. These losses are proportional to (f)(HV)2 and vary from insignificant to being a limiting factor on operating frequency in some high voltage applications.
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Paralleling MOSFETs When the above calculations result in a lower RDS(ON) than is economically feasible with a single MOSFET, two or more MOSFETs can be paralleled. The MOSFETs will inherently share the currents according to their RDS(ON) ratio as long as they are thermally connected (e.g., on a common heat sink). The LT1160 top and bottom drivers can each drive five power MOSFETs in parallel with only a small loss in switching speeds (see Typical Performance Characteristics). A low value resistor (10 to 47) in series with each individual MOSFET gate may be required to "decouple" each MOSFET from its neighbors to prevent high frequency oscillations (consult manufacturer's recommendations). If gate decoupling resistors are used the corresponding gate feedback pin can be connected to any one of the gates as shown in Figure 1. Driving multiple MOSFETs in parallel may restrict the operating frequency to prevent overdissipation in the LT1160 (see the following Gate Charge and Driver Dissipation).
GATE DR LT1160 GATE FB R G* R G*
*OPTIONAL 10
1160 F01
Figure 1. Paralleling MOSFETs
Gate Charge and Driver Dissipation A useful indicator of the load presented to the driver by a power MOSFET is the total gate charge QG, which includes the additional charge required by the gate-to-drain swing. QG is usually specified for VGS = 10V and VDS = 0.8VDS(MAX). When the supply current is measured in a switching application, it will be larger than given by the DC electrical characteristics because of the additional supply current associated with sourcing the MOSFET gate charge: dQ dQ ISUPPLY = IDC + G + G dt TOP dt BOTTOM
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LT1160/LT1162
APPLICATIONS INFORMATION
The actual increase in supply current is slightly higher due to LT1160 switching losses and the fact that the gates are being charged to more than 10V. Supply Current vs Input Frequency is given in the Typical Performance Characteristics. The LT1160 junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LT1160IS is limited to less than 31mA from a 12V supply: TJ = 85C + (31mA)(12V)(110C/W) = 126C exceeds absolute maximum In order to prevent the maximum junction temperature from being exceeded, the LT1160 supply current must be verified while driving the full complement of the chosen MOSFET type at the maximum switching frequency. Ugly Transient Issues In PWM applications the drain current of the top MOSFET is a square wave at the input frequency and duty cycle. To prevent large voltage transients at the top drain, a low ESR electrolytic capacitor must be used and returned to the power ground. The capacitor is generally in the range of 25F to 5000F and must be physically sized for the RMS current flowing in the drain to prevent heating and premature failure. In addition, the LT1160 requires a separate 10F capacitor connected closely between Pins 1 and 5 (the LT1162 requires two 10F capacitors connected between Pins 1 and 5, and Pins 7 and 11). The LT1160 top source is internally protected against transients below ground and above supply. However, the gate drive pins cannot be forced below ground. In most applications, negative transients coupled from the source to the gate of the top MOSFET do not cause any problems. Switching Regulator Applications The LT1160 (or 1/2 LT1162) is ideal as a synchronous switch driver to improve the efficiency of step-down (buck) switching regulators. Most step-down regulators use a high current Schottky diode to conduct the inductor current when the switch is off. The fractions of the oscillator period that the switch is on (switch conducting) and off (diode conducting) are given by:
V Switch ON = OUT Total Period HV HV - VOUT Switch OFF = Total Period HV
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(
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Note that for HV > 2VOUT the switch is off longer than it is on, making the diode losses more significant than the switch. The worst case for the diode is during a short circuit, when VOUT approaches zero and the diode conducts the short-circuit current almost continuously. Figure 2 shows the LT1160 used to synchronously drive a pair of power MOSFETs in a step-down regulator application, where the top MOSFET is the switch and the bottom MOSFET replaces the Schottky diode. Since both conduction paths have low losses, this approach can result in very high efficiency (90% to 95%) in most applications. For regulators under 10A, using low RDS(ON) N-channel MOSFETs eliminates the need for heat sinks. RGS holds the top MOSFET off when HV is applied before the 12V supply. One fundamental difference in the operation of a stepdown regulator with synchronous switching is that it never becomes discontinuous at light loads. The inductor current doesn't stop ramping down when it reaches zero but actually reverses polarity resulting in a constant ripple current independent of load. This does not cause a significant efficiency loss (as might be expected) since the negative inductor current is returned to HV when the switch turns back on. However, I2R losses will occur under these conditions due to the recirculating currents. The LT1160 performs the synchronous MOSFET drive in a step-down switching regulator. A reference and PWM are required to complete the regulator. Any voltage mode or current mode PWM controller may be used but the LT3526 is particularly well-suited to high power, high efficiency applications such as the 10A circuit shown in Figure 4. In higher current regulators a small Schottky diode across the bottom MOSFET helps to reduce reverse-recovery switching losses.
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LT1160/LT1162
APPLICATIONS INFORMATION
HV BOOST SV + 12V REF PWM T SOURCE OUT A OUT A IN TOP B GATE DR PV
+
LT1160
IN BOTTOM B GATE FB
Figure 2. Adding Synchronous Switching to a Step-Down Switching Regulator
Motor Drive Applications In applications where rotation is always in the same direction, a single LT1160 controlling a half-bridge can be used to drive a DC motor. One end of the motor may be connected either to supply or to ground as seen on Figure 3. A motor in this configuration is controlled by its inputs which give three alternatives: run, free running stop (coasting) and fast stop ("plugging" braking, with the motor shorted by one of the MOSFETs). To drive a DC motor in both directions the LT1162 can be used to drive an H-bridge output stage. In this configuration the motor can be made to run clockwise, counterclockwise, stop rapidly ("plugging" braking) or free run (coast) to a stop. A very rapid stop may be achieved by reversing the current, though this requires more careful design to stop the motor dead. In practice a closed-loop control system with tachometric feedback is usually necessary.
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T GATE DR T GATE FB RGS RSENSE
+
VOUT
1160 F02
The motor speed in these examples can be controlled by switching the drivers with pulse width modulated square waves. This approach is particularly suitable for microcomputers/DSP control loops.
HV LT1160 SV + 12V PV + BOOST T GATE DR T GATE FB T SOURCE IN TOP IN BOTTOM B GATE DR B GATE FB PGND
1160 F03
Figure 3. Driving a Supply Referenced Motor
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LT1160/LT1162
TYPICAL APPLICATIONS
C1 0.1F 4.7k 360 0.1F 4.7k 1 2 2k 0.33F 3 4 0.022F 1F 510 0.1F 5 6 7 8 9 27k f = 25kHz LT3526 16 15 14 13 12 11 10 2.2nF 1N4148 5k 1k 2N2222 6 7 1k 18 10F 17 1N4148 LT1160 1 2 3 4 5 SV + IN TOP BOOST T GATE DR 14 13 12 11 0.1F 330k L* 70H RS** 0.007 5V IRFZ44 1N4148
SHUTDOWN
* MAGNETICS CORE #55585-A2 30 TURNS 14GA MAGNET WIRE
Figure 4. 90% Efficiency, 40V to 5V 10A Low Dropout Voltage Mode Switching Regulator
1 2.2F 2k 10k 2 3 4 1F 18k 0.1F LT1846 5 6 6800pF 100pF 8 500k 18k 4700pF f = 40kHz 25k 7
16 15 14 13 12 11 10 9 10k 1N4148 1N4148 1k
* HURRICANE LAB HL-KM147U
** DALE TYPE LVR-3 ULTRONIX RCS01
Figure 5. 90% Efficiency, 40V to 5V 10A Low Dropout Current Mode Switching Regulator
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12
U
+
1F
12V
+
+
60V MAX 2200F EA LOW ESR
IN BOTTOM T GATE FB UV OUT SGND PGND NC T SOURCE
10 PV + B GATE DR B GATE FB 9 8
+
IRFZ44 IRFZ44 MBR360
5400F LOW ESR
** DALE TYPE LVR-3 ULTRONIX RCS01
1160/62 F04
12V 1N4148 10F 1 2 3 4 5 5k 1k 2N2222 6 7 SV + IN TOP 2200F EA LOW ESR 60V MAX
+
LT1160 BOOST T GATE DR 14 13 12 11 10 IRFZ44 9 0.1F
+
IRFZ44 330k L* 47H RS** 0.007 5V
IN BOTTOM T GATE FB UV OUT SGND PGND NC T SOURCE PV + B GATE DR B GATE FB
+
IRFZ44 MBR360
5400F LOW ESR
8
1160/62 F05
LT1160/LT1162
TYPICAL APPLICATIONS
100F IN 1k
10k 0.0033F
5V 0.1F 1k 1 2 3 1k 100k 4 LT1015 8 7 6 5 1 2 3 4 TC4428 8 7 6 5 0.1F
1k 1 2 LT1016 3 1F 0.1F 4 10k 1k 0.0033F 1 47F 2 3 47F 10k 10k 95k 4 5 200k 6 7 LT1058 13 12 11 10 9 8 14
Kool M is a registered trademark of Magnetics, Inc.
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U
150k
12V 10F 1N4148 LT1162 1 2 3 4 5 8 7 6 5 10F 6 7 8 9 10 11 10k 150k 10k 12 SV + A IN TOP A IN BOTTOM A UV OUT A GND A B GATE FB A SV + B IN TOP B IN BOTTOM B UV OUT B GND B B GATE FB B BOOST A T GATE DR A T GATE FB A T SOURCE A PV + A B GATE DR A BOOST B T GATE DR B T GATE FB B T SOURCE B PV + B B GATE DR B
60V MAX
1000F
+
24 IRFZ44 23 22 21 20 19 18 IRFZ44 17 16 15 14 IRFZ44 13 10F 0.1F 330k LOAD L* 158H 1000F 1N4148 IRFZ44 L* 158H 10F 0.1F 330k
-12V
0.1F 47F 10k
95k * Kool M(R) CORE #77548-A7 35 TURNS 14GA MAGNET WIRE fCARRIER = 100kHz
+
200k
47F 10k
1160/62 F06
Figure 6. 200W Class D, 10Hz to 1kHz Amplifier
13
LT1160/LT1162
PACKAGE DESCRIPTION
N Package 14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770* (19.558) MAX 14 13 12 11 10 9 8
.300 - .325 (7.620 - 8.255)
.008 - .015 (0.203 - 0.381) +.035 .325 -.015 +0.889 -0.381 .005 (0.125) .100 MIN (2.54) BSC
(
8.255
)
INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
NOTE: 1. DIMENSIONS ARE
.300 - .325 (7.620 - 8.255)
.008 - .015 (0.203 - 0.381)
(
+.035 .325 -.015 +0.889 8.255 -0.381
)
INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
NOTE: 1. DIMENSIONS ARE
14
U
.255 .015* (6.477 0.381)
1 .130 .005 (3.302 0.127) .020 (0.508) MIN
2
3
4
5
6
7
.045 - .065 (1.143 - 1.651)
.065 (1.651) TYP .120 (3.048) MIN .018 .003 (0.457 0.076)
N14 1002
N Package 24-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
1.265* (32.131) MAX 24 23 22 21 20 19 18 17 16 15 14 13
.255 .015* (6.477 0.381)
1 .130 .005 (3.302 0.127) .020 (0.508) MIN
2
3
4
5
6
7
8
9
10
11
12
.045 - .065 (1.143 - 1.651)
.065 (1.651) TYP .018 .003 (0.457 0.076)
.120 (3.048) MIN
.100 (2.54) BSC
N24 1002
OBSOLETE PACKAGE
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LT1160/LT1162
PACKAGE DESCRIPTION
S Package 14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.050 BSC N 14 13
.245 MIN
1 .030 .005 TYP
2
3
RECOMMENDED SOLDER PAD LAYOUT 1 .010 - .020 x 45 (0.254 - 0.508) 2 3 4 5 6 7
.008 - .010 (0.203 - 0.254)
.016 - .050 (0.406 - 1.270)
NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
.045 .005
.337 - .344 (8.560 - 8.738) NOTE 3 12 11 10 9 8
N .160 .005 .228 - .244 (5.791 - 6.197) N/2 N/2 .150 - .157 (3.810 - 3.988) NOTE 3
.053 - .069 (1.346 - 1.752)
0 - 8 TYP
.004 - .010 (0.101 - 0.254)
.014 - .019 (0.355 - 0.483) TYP
.050 (1.270) BSC
S14 0502
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15
LT1160/LT1162
PACKAGE DESCRIPTION
SW Package 24-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.030 .005 TYP N
.050 BSC .045 .005 .598 - .614 (15.190 - 15.600) NOTE 4 20 19 18 17 16
.420 MIN
1
2
3
N/2
RECOMMENDED SOLDER PAD LAYOUT .291 - .299 (7.391 - 7.595) NOTE 4 .010 - .029 x 45 (0.254 - 0.737)
0 - 8 TYP
.005 (0.127) RAD MIN
.009 - .013 (0.229 - 0.330) NOTE: 1. DIMENSIONS IN
NOTE 3 .016 - .050 (0.406 - 1.270)
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
RELATED PARTS
PART NUMBER LT1158 LT1336 LT1910 LTC1922-1 LTC1923 DESCRIPTION Half-Bridge N-Channel Power MOSFET Driver Half-Bridge N-Channel Power MOSFET Driver with Boost Regulator Protected High Side MOSFET Driver Synchronous Phase Modulated Full-Bridge Controller Full-Bridge Controller for Thermoelectric Coolers COMMENTS Single Input, Continuous Current Protection and Internal Charge Pump for DC Operation Onboard Boost Regulator to Supply the High Side Driver VIN = 8V to 48V, Protected from -15V to 60V Transients, Auto Restart, Fault Indication Output Power from 50W to Kilowatts, Adaptive Direct Sense Zero Voltage Switching Compensates for External Component Tolerances High Efficiency, Adjustable Slew Rate Reduces EMI 5mm x 5mm QFN and 28-Pin SSOP
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
U
24
23
22
21
15
14
13
N .325 .005 NOTE 3 .394 - .419 (10.007 - 10.643)
N/2
1 .093 - .104 (2.362 - 2.642)
2
3
4
5
6
7
8
9
10
11
12 .037 - .045 (0.940 - 1.143)
.050 (1.270) BSC
.004 - .012 (0.102 - 0.305)
.014 - .019 (0.356 - 0.482) TYP
S24 (WIDE) 0502
LT 0807 REV B * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 1995

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